```
all: compile simulate
compile:
vcs \\
-sverilog \\
-debug\_all \\
-l com.log \\
-f rtl.lst
simulate:
./simv -l sim.log
clean:
@rm -rf csrc DVEfiles simv simv.daidir ucli.key VCS\*
@rm -rf \*.log \*.vpd \*.ddc \*.svf \*.SDF \*Synth \*Netlist\*
@rm -rf alib-52
```
