latch · Verilog

## 锁存器 ![](https://img.kancloud.cn/76/ab/76abf5133de7ca389149dcb964c12f2d_452x126.png) ``` always@(D, ena1) begin if (ena1==1'b1) QsimpleReg <= D; end ``` ![](https://img.kancloud.cn/40/97/4097164a645917562358c5533d2271d1_536x165.png) ![](https://img.kancloud.cn/0b/cf/0bcf4b8780ab2f33c522bdeb86c8a076_848x309.png)